1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) with an improved memory cell pattern layout.
2. Description of the Related Art
One known EEPROM in the field of semiconductor memory devices is a NAND-cell EEPROM enabling large-scale integration. A NAND cell has the following configuration.
A plurality of memory cells are arranged in the column direction, for example. Of these memory cells, the sources and drains of adjacent memory cells are shared and connected in series one after another. Connecting in this way forms unit cell groups (NAND cells) where a plurality of memory cells are connected in series. Each unit cell group, treated as a unit, is connected to a corresponding bit line via a select gate having an FETMOS structure.
A memory cell has an FETMOS structure where a floating gate, serving as a charge storage layer and a control gate are stacked. These gates and memory cells are integrated into an array in a p-well formed in an n-type substrate. The drain of a NAND cell is connected to a bit line via the select gate, and the source of the NAND cell is connected to another source line (another reference potential line) via a select gate. The control gate of each memory cell is connected to corresponding word line, where each word line is arranged in the row direction.
FIG. 1 is a layout diagram of conventional memory cells. The figure only shows diffusion layers 1 acting as sources and drains, tungsten polycides 2, which is a film composed of polysilicon and metal, serving as source lines, Al wire layers 3 serving as bit lines, and contacts 4 between the Al layers 3 and the tungsten polycides 2 or the diffusion layers 1.
The source diffusion layer of every other NAND cell is brought into contact with a tungsten polycide, thereby lowering the source resistance. However, when memory cells are made finer and the lateral or vertical cell size becomes smaller, Al bit lines cannot be patterned under the minimum design rules in terms of lithography and processing.
The reason will be described below.
In the prior art, the minimum line width and interval of tungsten polycides are 0.55 .mu.m or 0.6 .mu.m, the minimum size of the contact between a tungsten polycide and a diffusion layer is 0.6 .mu.m.times.0.7 .mu.m, the minimum Al wire width and its interval are 0.8 .mu.m, and the minimum size of the contact between Al and a diffusion layer is 0.8 .mu.m.times.0.9 .mu.m. Therefore, the size of an Al wire portion is greater than that of a tungsten polycide.
The contact portion of Al and a diffusion layer is a serious hindrance to miniaturize memory cells, since its aspect ratio is larger than that of the contact between a polycide and a diffusion layer. Furthermore, since an Al layer has a thickness of 800 nm, thicker than that of a polycide, the coupling capacity between bit lines is greater, causing a faulty operation. Because a polycide wire to a source has larger resistance than an Al wire, it takes longer time to discharge a cell current during a reading operation. In addition, since a shunt portion 5 to be in contact with an Al wire is needed for a specific number of cells, this makes the chip area larger.
As described above, since the conventional EEPROM including NAND cell uses Al wires as bit lines, it is necessary to make the wire width, the distance between wires, and the contact size relatively larger, thus hindering the memory cells from being made finer. Furthermore, the Al wires must be made thicker so as to be in contact with the underlying layer, causing faulty operation due to coupling noise between the bit lines.